In the fabrication of integrated circuits upon semiconductor substrates, highly miniaturized electronic devices are formed by patterning layers of various materials upon each other. In many instances these layers or portions of layers are grown upon existing layers of material or the substrate itself and a particular concern is the stresses that build up at the interface of the layers when one is grown or deposited upon another.
In many isolation schemes used to isolate devices from one another, such as local oxidation of silicon (LOCOS), sealed interface local oxidation (SILO), etc., the oxidation masking layers such as Si.sub.3 N.sub.4 on top of SiO.sub.2, which is used for LOCOS, together with the volume expansion of the field oxidation being grown can induce mechanical stresses in the underlying silicon which exceed its elastic limit and thereby create dislocations and other crystallographic defects. In fact, the stress has been shown to be highest at the edge of the masking structure, see K. Shibata, et al. "Generation Mechanism of Dislocations in Local Oxidation of Silicon," J. Electrochem. Soc., Vol. 127, No. 6, 1980, pp. 1383-1387 and C. Claeys, et al. "Defect Control in Si.sub.3 N.sub.4 /SiO.sub.2 Structures for Isolation Techniques", paper publication 1984, pp. 272-287. If these defects occur at or near a p/n junction, junction leakage may occur and device degradation will result. Investigations into eliminating these problems have determined that the oxygen concentration of the silicon wafer is important in determining its resistance to plastic deformation during events such as field oxide growth.
In epitaxial layers, which are grown or deposited on the surface of a semiconductor wafer, the resistance to plastic deformation is less than that of typical Czochralski silicon wafers because the epitaxial (epi) layers are essentially oxygen-free. For example, in one study of the micro-hardness of epitaxial v. non-epitaxial wafers, the non-epitaxial wafers were measured as being appreciably harder. The numbers shown below are based on measurements of essentially how deep into the surface a standard indentation probe penetrated, factored into a calculation such that the smaller the result, the softer the surface (Knoop hardness).
TABLE I ______________________________________ Hardness Measurements (average of ten readings each) Knoop Hardness Index ______________________________________ 1. 14 micron (.mu.m) thick p.sup.- epi of 14-22 ohm-cm 769 resistivity on p.sup.+ wafer of 0.01-0.02 ohm-cm resistivity 2. p.sup.- wafer of 14-22 ohm-cm resistivity and 854 nominally 28 ppm oxygen ______________________________________
This data leads to the speculation that junction leakage resulting from silicon defects could be more severe when fabricated in epitaxial layers than bulk silicon.